JPH0223060B2 - - Google Patents

Info

Publication number
JPH0223060B2
JPH0223060B2 JP56051117A JP5111781A JPH0223060B2 JP H0223060 B2 JPH0223060 B2 JP H0223060B2 JP 56051117 A JP56051117 A JP 56051117A JP 5111781 A JP5111781 A JP 5111781A JP H0223060 B2 JPH0223060 B2 JP H0223060B2
Authority
JP
Japan
Prior art keywords
station
address
input
output
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56051117A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57166759A (en
Inventor
Hiroshi Kobayashi
Hiroaki Nakanishi
Hideo Yanai
Yasushi Fukunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56051117A priority Critical patent/JPS57166759A/ja
Publication of JPS57166759A publication Critical patent/JPS57166759A/ja
Publication of JPH0223060B2 publication Critical patent/JPH0223060B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks

Landscapes

  • Small-Scale Networks (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP56051117A 1981-04-07 1981-04-07 Controlling method for common input/output bus Granted JPS57166759A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56051117A JPS57166759A (en) 1981-04-07 1981-04-07 Controlling method for common input/output bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56051117A JPS57166759A (en) 1981-04-07 1981-04-07 Controlling method for common input/output bus

Publications (2)

Publication Number Publication Date
JPS57166759A JPS57166759A (en) 1982-10-14
JPH0223060B2 true JPH0223060B2 (en]) 1990-05-22

Family

ID=12877858

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56051117A Granted JPS57166759A (en) 1981-04-07 1981-04-07 Controlling method for common input/output bus

Country Status (1)

Country Link
JP (1) JPS57166759A (en])

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58130647A (ja) * 1982-01-29 1983-08-04 Nec Corp ル−プ式デ−タ伝送方式
JPS5986353A (ja) * 1982-11-09 1984-05-18 Toshiba Corp デ−タ伝送装置
JPS59228444A (ja) * 1983-06-10 1984-12-21 Canon Inc 通信方式
JPS61145670A (ja) * 1984-12-19 1986-07-03 Nec Corp マルチプロセツサシステム

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5336120A (en) * 1976-09-16 1978-04-04 Fujitsu Ltd Information transfer system
JPS54163607A (en) * 1978-06-15 1979-12-26 Nissin Electric Co Ltd Data sorting system

Also Published As

Publication number Publication date
JPS57166759A (en) 1982-10-14

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